Intel CPU microcode applied at boot to patch processor errata and hardware security issues.
Version: 20260812
Type: Firmware
License:
| Expand | CVE | Title | Status | Sev |
|---|---|---|---|---|
| CVE-2025-31648 Open CVE-2025-31648 in a new tab | Improper handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privilege. | Not affected | Unknown | |
| CVE-2025-31936 Open CVE-2025-31936 in a new tab | Improper handling of overlap between protected memory ranges for some Intel(R) Xeon(R) 6 processors when using Intel(R) TDX within SMM may allow an escalation o… | Not affected | Unknown | |
| CVE-2025-31938 Open CVE-2025-31938 in a new tab | Insufficient granularity of access control in some subsystem for some Intel(R) Xeon(R) 6 Scalable processors with Intel(R) TDX may allow an information disclosu… | Not affected | Unknown | |
| CVE-2025-35973 Open CVE-2025-35973 in a new tab | Improper handling of values for some Intel(R) Processors within Ring 0: Kernel, Hypervisor and Bare Metal OS may allow an escalation of privilege. | Not affected | Unknown | |
| CVE-2025-35979 Open CVE-2025-35979 in a new tab | Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution for some Intel(R) Processors within VM… | Not affected | Unknown | |
| CVE-2026-20707 Open CVE-2026-20707 in a new tab | Hardware logic contains race conditions for some 3rd Gen Intel(R) Xeon(R) Scalable Processors within Ring 3: unprivileged software may allow a denial of service… | Not affected | Unknown | |
| CVE-2026-20713 Open CVE-2026-20713 in a new tab | Always-incorrect control flow implementation in some firmware for some Intel(R) Xeon(R) processors may allow an escalation of privilege. | Not affected | Unknown | |
| CVE-2026-20716 Open CVE-2026-20716 in a new tab | Improper access control for some Intel(R) Processors within Ring 3: User Applications may allow an escalation of privilege. | Not affected | Unknown | |
| CVE-2026-20760 Open CVE-2026-20760 in a new tab | Improper handling of overlap between protected memory ranges in some microcode for some Intel(R) Processors within Ring 0: Hypervisor may allow an escalation of… | Not affected | Unknown | |
| CVE-2026-20901 Open CVE-2026-20901 in a new tab | Improper input validation for some Intel(R) Xeon(R) processors within firmware may allow an escalation of privilege. | Not affected | Unknown | |
| CVE-2026-20917 Open CVE-2026-20917 in a new tab | Exposure of sensitive information caused by incorrect data forwarding during transient execution for some Intel(R) Processors within Ring 0: Hypervisor and Kern… | Not affected | Unknown |
Improper handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privilege.
Improper handling of overlap between protected memory ranges for some Intel(R) Xeon(R) 6 processors when using Intel(R) TDX within SMM may allow an escalation o…
Insufficient granularity of access control in some subsystem for some Intel(R) Xeon(R) 6 Scalable processors with Intel(R) TDX may allow an information disclosu…
Improper handling of values for some Intel(R) Processors within Ring 0: Kernel, Hypervisor and Bare Metal OS may allow an escalation of privilege.
Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution for some Intel(R) Processors within VM…
Hardware logic contains race conditions for some 3rd Gen Intel(R) Xeon(R) Scalable Processors within Ring 3: unprivileged software may allow a denial of service…
Always-incorrect control flow implementation in some firmware for some Intel(R) Xeon(R) processors may allow an escalation of privilege.
Improper access control for some Intel(R) Processors within Ring 3: User Applications may allow an escalation of privilege.
Improper handling of overlap between protected memory ranges in some microcode for some Intel(R) Processors within Ring 0: Hypervisor may allow an escalation of…
Improper input validation for some Intel(R) Xeon(R) processors within firmware may allow an escalation of privilege.
Exposure of sensitive information caused by incorrect data forwarding during transient execution for some Intel(R) Processors within Ring 0: Hypervisor and Kern…